In recent electronic equipment, there have been an increased number of electronic equipment having a battery backup mode in order that set conditions of the internal or operating results, etc. can be retained even at the time when a main power supply is cut OFF. In the battery backup mode, so called a backup battery is used as its power supply. For this reason, particularly not only for a time period in a battery backup mode, but also in the middle of shift from an ordinary operational mode by the main power supply to the battery backup mode, the current consumption is required to be as small as possible. CMOS type devices hardly consume a current in a static state on the basis of the basic structure and the principle of operation. By drawing attention to this fact, with a view to retaining data at the time of battery backup, it is ordinary practice that CMOS type devices are used.
FIG. 1 shows a basic structure of an electronic equipment having a battery backup mode using a CMOS device as described above.
As seen from this figure, in an ordinary operational mode, the power is delivered from a main power supply 3 to all the system components, i.e., a CMOS device 1 for retaining data and circuitry 5 for other devices or equipment, etc. necessary to be supplied with a power.
On the other hand, in a battery backup mode, i.e., when the main power supply 3 is cut OFF by power supply switches 4, a power is delivered from a backup battery 2 only to the CMOS device 1 for retaining data.
In such a prior art, the problem as described below arises at the time of shift from the ordinary operational mode to the battery backup mode. Namely, in the middle of the mode shift, a through current flows in the input buffer section of the device 1. For this reason, the battery may be consumed. The mechanism of this problem will be described as follows. Namely, generally the input buffer of the CMOS device includes a CMOS inverter comprised of a P-channel MOS transistor Tr1 and an N-channel MOS transistor Tr2 connected in series as shown in FIG. 2. Accordingly, when zero volts or a power supply voltage Vcc is applied to the input terminal IN, one of the P-channel transistor Tr1 and the N-channel transistor Tr2 is turned ON and the other thereof is turned OFF. Because either transistor is cut OFF as stated above, no d.c. current is consumed. However, when an intermediate potential between zero volts and Vcc is applied to the input terminal IN, the transistors Tr1 and Tr2 are both turned ON. As a result, the so called through current flows. Accordingly, in the process of the mode shift from the ordinary operational mode to the battery backup mode, where the interface section from the circuit 5 to the device 1 is placed at an intermediate potential for any reason, a through current flows, giving the cause of consumption of the battery as previously described. By inserting a pull-up resistor in the input buffer circuit of FIG. 2, an improvement is made to some extent. However, ordinarily the pull-up resistor of the equipments which use CMOS device is more than several K.OMEGA. because of output buffer current characteristics. For this reason, where the intermediate potential of the circuit 5 in FIG. 1 is kept for a relatively long time at an impedance lower than the pull-up resistance, the effect of the pull-up resistor is not sufficient.